Product Summary

The MC74HC138ADR2G is a 1-of-8 Decoder/Demultiplexer. The device inputs are compatible with standard CMOS outputs; with pull up resistors, they are compatible with LSTTL outputs. The MC74HC138ADR2G decodes a three-bit Address to one-of-eight active low outputs. The MC74HC138ADR2G features three Chip Select inputs, two active-low and one active-high to facilitate the demultiplexing, cascading, and chip-selecting functions. The demultiplexing function is accomplished by using the Address inputs to select the desired device output; one of the Chip Selects is used as a data input while the other Chip Selects are held in their active states.

Parametrics

MC74HC138ADR2G absolute maximum ratings: (1)DQ Supply Voltage (Referenced to GND), VCC: -0.5 to +7.0V; (2)DQ Input Voltage (Referenced to GND), Vin: -0.5 to Vqq +0.5V; (3)DQ Output Voltage (Referenced to GND), Vout: -0.5 to Vqq +0.5V; (4)DQ Input Current, per Pin, Iin: ±20mA; (5)DQ Output Current, per Pin, Iout: ±25mA; (6)DQ Supply Current, Vqq and GND Pins, IQQ: ±50mA; (7)Power Dissipation in Still Air, Plastic DIP, PD: 750mW; SOIQ Package, PD: 500mW; TSSOP Package, PD: 450mW; (8)Storage Temperature, Tstg: -65 to +150℃; (9)Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP, SOIQ or TSSOP Package), Tl: 260℃.

Features

MC74HC138ADR2G features: (1)Output Drive Capability: 10 LSTTL Loads; (2)Outputs Directly Interface to CMOS, NMOS and TTL; (3)Operating Voltage Range: 2.0 to 6.0 V; (4)Low Input Current: 1.0 μA; (5)High Noise Immunity Characteristic of CMOS Devices; (6)In Compliance with the Requirements Defined by JEDEC Standard No. 7A; (7)Chip Complexity: 100 FETs or 29 Equivalent Gates; (8)Pb-Free Packages are Available.

Diagrams

MC74HC138ADR2G block diagram

Image Part No Mfg Description Data Sheet Download Pricing
(USD)
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MC74HC138ADR2G
MC74HC138ADR2G

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Data Sheet

0-1: $0.22
1-25: $0.17
25-100: $0.11
100-500: $0.09
Image Part No Mfg Description Data Sheet Download Pricing
(USD)
Quantity
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